IBM Debuts World’s First Sub‑1 Nanometer Chip Technology

IBM announced the world’s first sub‑1 nm chip, built at a 0.7 nm (7 Å) node using a revolutionary three‑dimensional nanostack architecture. The chip packs nearly 100 billion transistors on a fingernail‑sized die, roughly twice the density of IBM’s 2 nm chip unveiled in 2021. The nanostack design vertically stacks and staggers transistors, allowing different material combinations in each layer to optimize performance and power independently. Experimental validation demonstrated dual‑channel engineering, functional CMOS inverter operation, and a 40 % scaling in SRAM, enabling more efficient chips for high‑bandwidth AI workloads. IBM projects the technology to deliver up to 50 % performance gains and 70 % greater energy efficiency compared to the 2 nm node, with potential production within the next five years.

The breakthrough extends logic technology below the 1 nm node, marking a new era of angstrom‑level scaling where dimensions approach atomic sizes. IBM’s roadmap projects at least a decade of future scaling, supported by upcoming High‑NA EUV lithography tools and collaborations with industry partners such as Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. The announcement also highlighted IBM’s plan to form Anderon, a pure‑play quantum foundry, further positioning the company at the forefront of semiconductor and quantum computing innovation.

Enterprise customers and AI workloads stand to benefit from the chip’s unprecedented density and efficiency, potentially reshaping cloud infrastructure, generative AI, and next‑generation electronic devices.